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1. general description the tda8035 is the cost efficient successor of the well established integrated contact smart card reader ic tda8024. it offers a high level of security for the card performing current limitation, short circui t detection, esd protection as well as supply supervision. operating in 3 v supply domain, the current consumption during the standby mode of the contact reader is very low and is therefor e the ideal component for a power efficient contact reader. 2. features and benefits 2.1 protection of the contact smart card ? thermal and short-circuit prot ections on all card contacts ? vcc regulation: ? 5 v, 3 v, 1.8 v 5 % on 2 220 nf multilayer ceramic capacitors with low esr ? current spikes of 40 na/s (vcc = 5 v and 3 v) or 15 na/s (vcc = 1.8 v) up to 20 mhz, with controlled rise and fall times, filtered overload detection approximately 120 ma ? automatic activation and deactivation sequen ces initiated by software or by hardware in the event of a short-circuit, ca rd take-off, overheating, falling v reg v dd(intf), v ddp ? enhanced card-side electrostatic discharge (esd) protection of (> 8 kv) ? supply supervisor for killing spik es during power on and off: ? threshold internally fixed ? externally by a resistor bridge 2.2 easy integration into your contact reader ? sw compatible to tda8024 and tda8034 ? 5 v, 3 v, 1.8 v smart card supply ? dc/dc converter for vcc generation separately powered from 2.7 v to 5.5 v supply (vddp and gndp) ? very low power consumption in deep shutdown mode ? three protected half-duplex bidirectional buffered i/o lines (c4, c7 and c8 ) ? external clock input up to 26 mhz ? card clock generation up to 20 mhz using pins clkdiv1 and clkdiv2 with synchronous frequency changes of f xtal, f xtal/2, f xtal/4 or f xtal/8 ? non-inverted control of pin rst using pin rstin ? built-in debouncing on card presence contact ? multiplexed status signal using pin offn TDA8035HN smart card interface rev. 1.0 ? 19 april 2011 product data sheet
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 2 of 32 nxp semiconductors TDA8035HN smart card interface ? chip select digital input for paralle l operation of several tda8035 ics. 2.2.1 other ? hvqfn32 package ? compliant with iso 7816, nds and emv 4.2 payment systems 3. applications ? pay tv ? electronic payment ? identification ? ic card readers for banking 4. quick reference data table 1. quick reference data v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb = 25 c; unless otherwise specified symbol parameter conditions min typ max unit supply v ddp power supply voltage 2.7 3.3 5.5 v v dd(intf) interface supply voltage 1.6 3.3 3.6 v i ddp power supply current deep shutdown mode; f xtal = stopped; -0.13 a shutdown mode; f xtal = stopped; - 300 500 a active mode; v cc = +5 v clk = f xtal /2; no load --5 ma active mode; clk = f xtal /2 ; v cc = +5 v; icc = 65 ma - - 220 ma active mode; clk = f xtal /2 ; v cc = +3 v; i cc = 65 ma - - 160 ma active mode; clk = f xtal /2 ; v cc = +1.8 v; icc = 35 ma - - 120 ma i dd(intf) interface supply current deep shutdown mode; f xtal = stopped; present card --1 a shutdown mode; f xtal = stopped; present card --1 a internal supply voltage v dd supply voltage 1.62 1.8 1.98 v card supply voltage: pin v cc
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 3 of 32 nxp semiconductors TDA8035HN smart card interface 5. ordering information v cc supply voltage 5 v card; dc i cc < 65 ma 4.75 5.0 5.25 v 5 v card; ac current spikes of 40 nas 4.65 5.0 5.25 v 3 v card; dc i cc < 65 ma 2.85 - 3.15 v 3 v card; ac current spikes of 40 nas 2.76 - 3.24 v 1.8 v card; dc i cc < 35 ma 1.71 - 1.89 v 1.8 v card; ac current spikes of 15 nas 1.66 - 1.94 v v ripple(p-p) peak-to-peak ripple voltage from 20 khz to 200 mhz - - 300 mv i cc supply current v cc = 5 v or 3 v - - 65 ma v cc = 1.8 v - - 35 ma general t deact deactivation time total sequence 35 90 250 s p tot total power dissipation t amb = ? 40 cto+85 c--0.45w t amb ambient temperature -25 - +85 c table 1. quick reference data ?continued v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb = 25 c; unless otherwise specified symbol parameter conditions min typ max unit table 2. ordering information type number package name description version TDA8035HN/c1 hvqfn32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 sot617-7
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 4 of 32 nxp semiconductors TDA8035HN smart card interface 6. block diagram fig 1. block diagram 001aan745 10 f 1 f 2 220 nf 100 nf 100 nf 100 nf 330 nf cmdvccn en_5v/3vn en_1.8vn rstin clkdiv1 clkdiv2 iouc aux1uc aux2uc offn internal regulator supervisor input sense deep shutdown deep shutdown deep shutdown bandgap host interface latch cs configurations bus for smartcard reader interface interuption reset and supalarm h z h z vddi internal oscillator thermal protection digital sequencer tda8035 dcdc converter gndp gnd vddp vreg poradj v dd(intf) v dd(intf) vddp sam vcc gndc rst clk aux1 aux2 xtal1 xtal2 presn io sap 330 nf sbm vup c1 sbp iso7816 reader interface crystal oscillator uc c5 c2 c6 c3 c7 c4 c8
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 5 of 32 nxp semiconductors TDA8035HN smart card interface 7. pinning information 7.1 pinning 7.2 pin description fig 2. pin configuration hvqfn32 i/ouc clk poradj rst cmdvccn vcc vdd(intf) vup clkdiv1 sap clkdiv2 sbp en_5v/3vn vddp en_1.8vn sbm rstn aux2uc offn aux1uc gnd presn xtal1 cs xtal2 i/o vreg aux2 sam aux1 gndp gndc tda8035 001aan746 transparent top view terminal 1 index area 8 17 7 18 6 19 5 20 4 21 3 22 9 10 11 12 13 14 32 31 30 29 28 27 15 26 16 25 2 23 1 24 table 3. pin description symbol pin supply type description i/ouc 1 v dd(intf) i/o host data i/o line (internal 10k pullup resistor to v dd(intf) ) poradj 2 v dd(intf) i input for v dd(intf) supervisor. poradj threshold can be changed with an external r bridge cmdvccn 3 v dd(intf) i start activation sequence input from the host (active low) v dd(intf) 4v dd(intf) supply interface supply voltage clkdiv1 5 v dd(intf) i control with clkdiv2 for choosing clk frequency see ta b l e 4 clkdiv2 6 v dd(intf) i control with clkdiv1 for choosing clk frequency see ta b l e 4 en_5v/3vn 7 v dd(intf) i control signal for selecting vcc = 5 v (high) or vcc = 3 v (low) if en_1.8 vn = high en_1.8 vn 8 v dd(intf) i control signal for selecting vcc = 1.8v (low) rstin 9 v dd(intf) i card reset input from the host (active high) offn 10 v dd(intf) o nmos interrupt to the host (active low) with 10k internal pull up resistor to v dd(intf) (see fault detection) gnd 11 - supply ground xtal1 12 v dd(intf) i crystal connection xtal2 13 v dd(intf) o crystal connection vreg 14 v ddp supply internal supply voltage sam 15 v ddp i/o dc/dc converter capacitor ; connected between sam and sap; c = 330nf with esr < 100m gndp 16 - supply dc/dc converter power supply ground
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 6 of 32 nxp semiconductors TDA8035HN smart card interface sbm 17 v ddp i/o dc/dc converter capacitor ; connected between sbm and sbp; c = 330nf with esr < 100m v ddp 18 v ddp supply power supply voltage sbp 19 v ddp i/o dc/dc converter capacitor ; connected between sbm and sbp; c = 330nf with esr < 100m sap 20 v ddp i/o dc/dc converter capacitor ; connected between sam and sap; c = 330nf with esr < 100m vup 21 v ddp i/o dc/dc converter output decoupling capacitor connected between vup and gndp; c = 1uf with esr < 100m vcc 22 vcc o supply for the card (c1)( decouple to gnd with 2 220nf capacitors with esr < 100m ). rst 23 vcc o card reset (c2) clk 24 vcc o clock to the card (c3) gndc 25 - supply card signal ground aux1 26 vcc i/o auxiliary data line to/from the card (c4)(internal 10 k pull up resistor to vcc ) aux2 27 vcc i/o auxiliary data line to/from the card (c8)(internal 10 k pull up resistor to vcc ) i/o 28 vcc i/o data line to/from the card (c7)(internal 10 k pull up resistor to vcc ) cs 29 v dd(intf) i chip select input from the host ( active high ) presn 30 v dd(intf) i card presence contact input (active low); if presn is true, then the card is considered as present. a debouncing feature of 4.05 ms typ. is built in. aux1uc 31 v dd(intf) i/o auxiliary data line to/from the host (internal 10 k pull up resistor to v dd(intf) ) aux2uc 32 v dd(intf) i/o auxiliary data line to/from the host (internal 10 k pull up resistor to v dd(intf) ) table 3. pin description ?continued symbol pin supply type description
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 7 of 32 nxp semiconductors TDA8035HN smart card interface 8. functional description remark: throughout this document the iso 7816 terminology conventions have been adhered to and it is a ssumed that the reader is familiar with these. 8.1 power supply power supply voltage v ddp should be in the range from 2.7 to 5.5 v all interface signals with the system controller are referenced to v dd(intf) . all card contacts remain inactive during powering up or powering down. internal regulator vreg should be in the range of 1.8 v after powering the device, offn remains lo w until cmdvccn is set high and presn is low . during power off, offn falls low when v ddp is below the threshold voltage falling. the frequency of the inte rnal oscillator foscint used for th e activation sequences is put in low frequency mode in order to save power consumption as long as cmdvccn is kept at high level (card not activated). this device includes dc/dc converter to generate the 5 v, 3 v or 1.8 v card supply voltage (vcc). the dc/dc converter should be supplied separately by vddp and gndp. the dc/dc converter operates as a voltage tripler, doubler or follower according to the respective values of vcc and vddp. the operating mode is as follows (see figure 3 ): ? vcc = 5 v & vddp > 3.8 v ; voltage doubler ? vcc = 5 v & vddp < 3.6 v; voltage tripler ? vcc = 3 v & vddp > 3.8 v; voltage follower ? vcc = 3 v & vddp < 3.6 v; voltage doubler ? vcc = 1.8 v & vddp > 3.8 v; voltage doubler ? vcc = 1.8 v & vddp < 3.6 v; voltage tripler
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 8 of 32 nxp semiconductors TDA8035HN smart card interface 8.2 voltage supervisor the voltage supervisor is used as a power on reset, and also as supply drop detection during a card session. the threshold of the voltag e supervisor is set internally in the ic for v ddp and v reg whereas it can be adjusted externally for v dd(intf) using the poradj pin. as long as v reg is less than vth(v reg ) + vhys(v reg ), the ic will remain inactive whatever the levels on the command lines are. this also lasts for the duration of tw after v reg has reached a level higher than vth(v reg ) + vhys(v reg ).the outputs of the v ddp, v reg and v dd(intf) supervisors are combined and sent to a digital controller in order to reset the tda8035. this defined reset pulse of approximately 5.7 ms (tw=2048 1/(fosc(int)_low) is used internally for maintain ing the ic in a inactive mode during the supply voltage power-on; (see following pictures). when v reg falls below vth(v reg ) or when v dd(intf) falls below vthextf or when v ddp falls below vth(vddp) , a deactivation sequence is performed. fig 3. block voltage supervisor 001aan747 vbg vreg vddp vreg vbg vdd(intf) vbg poradj deep_shutdown
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 9 of 32 nxp semiconductors TDA8035HN smart card interface fig 4. voltage supervisor fig 5. voltage supervisor 001aan748 debouncing tw tw x x x x 180 khz 1.2 v x x vsup vt vth_vddp_ih supervisor outputs supervisor inputs ic pins reset 2 tw x supalarm deep_shutdown oscint vreg vddp vbg offn 001aan749 vddp vreg vsup vth_vddp_ih vth_vddp_hi 1 1 22 3 100 s analog delay 3 start debouncing if a card has been inserted during shutdown mode tw 2.65 v 2.5 v 1.8 v tw tw supalarm reset
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 10 of 32 nxp semiconductors TDA8035HN smart card interface 8.3 clock circuitry to generate the card clock clk, the tda8035 can either use an external clock provided on xtal1 pin or a crystal oscillator conn ected on both xtal1 and xtal2 pins. the tda8035 automatically detects if an external clock is provided on xtal1. so, there is no need of an extra pin to configure the clock source (external clock or crystal). the automatic clock source detection is performed on each activation command (cmdvccn pin falling edge). during a time wi ndow defined by the inte rnal oscillator, the presence of an external clock on xtal1 pin is checked. if a clock is detected, the crystal oscillator is kept stopped, else , the crystal oscillator is star ted. it is mandatory when an external clock is used, that the clock is applied on xtal1 before cmdvccn falling edge signal. the frequency may be chosen as f xtal , f xtal/2 , f xtal/4 or f xtal/8 via the pins clkdiv1 and clkdiv2. (both selection inputs shall not be changed simultaneously: 10 ns minimum are required between changes on clkdiv1/clkdiv2). the frequency change is synchronous, whic h means that during transition, no pulse is shorter than 45 % of the smallest period and that the first and last clock pulse around the change has the correct width. when changing dynamically the frequency, the change is effective only 10 periods of xtal1 after the command. the duty cycle on pin clk shall be between 45 % and 55 % : ? when an external clock is used on xtal1 pin , it should have a duty cycle of 48 % to 52 % when f xtal is used and rise and fall time s shall respect values mentioned on table 7 t r(i) , t f (i). it has to connect a 56 pf serial capacitor . ? clk frequency is f xtal ,f xtal/2, f xtal/4 or f xtal/8 : it is guaranteed between 45 % and 55 % of the period by the frequency dividers. fig 6. switch external clock table 4. clock configuration clkdiv1 clkdiv2 clk 00f xtal/8 01f xtal/4 11f xtal/2 10f xtal 001aan750 digital mux enclkin clkxtal xtal
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 11 of 32 nxp semiconductors TDA8035HN smart card interface 8.4 i/o circuitry the three data lines i/o, aux1 and aux2 are identical. the idle state is realized by both lines (i/o and i/ouc) being pulled high via a 10 k resistor (i/o to v cc and i/ouc to v dd(intf)) . i/o is referenced to v cc , and i/ouc to v dd(intf) , thus allowing operation with v cc v dd(intf) . the first side on which a fallin g edge occurs becomes the ma ster. an anti-latch circuit disables the detection of falling edges on the other line, which becomes a slave. after a time delay t d(edge) , the logic 0 present on the master side is transmitted to the slave side. when the master side returns to logic 1, the slave side transmits the logic 1 during the time delay tpu, and then both si des return to th eir idle states. this active pull-up feature ensures fast low to high transitions; it is able to deliver more than 1 ma up to an output voltage of 0.9 v cc on a 80 pf load. at the end of the active pull-up pulse, the output voltage only depends on the internal pull-up resistor, and on the load current. the current to/from the cards i/o lines is internally limited to 15 ma. the maximum frequency on these lines is 1.5 mhz.
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 12 of 32 nxp semiconductors TDA8035HN smart card interface 8.5 cs control the cs (chip select) input allows multiple de vices to operate in parallel. when cs is high, the system interface signals operate as described. when cs is low , the signals cmdvccn, rstin, clkdiv1, clkdiv2, en 5v/3vn and en1v8n are latched. i/ouc, aux1uc and aux2uc are set to high impedance pull up mode and won?t pass data to or from the smart card. offn output is tri-stated. 8.6 shutdown mode and deep shutdown mode after power-on reset, the circuit enters the shutdown mode if cmdvccn input pin is to a logic-high. a minimum number of circuits are active while waiting fo r the micro-controller to start a session. 1. all card contacts are inactive (approximately 200 to gnd). 2. i/ouc, aux1uc and aux2uc are high impedance (10 k pull-up resistor connected to v ddi ). 3. voltage generators are stopped. 4. voltage supervisor is active. 5. the internal oscillator ru ns at its low frequency. a deep shutdown mode can be entered by forcing cmdvccn input pin to a logic-high state and en5v/3vn, en1v8n input pins to a logic-low state. deep shutdown mode can only be entered when the smart card reader is inactive. in deep shutdown mode, all circuits are disabled. the offn pin follows the status of presn pin. to exit deep shutdown mode, change the state of one or more of the three control pins. figure 8 shows the control sequence for entering and exiting. fig 7. shutdown mode and deep shutdown mode 001aan751 cmdvccn deactivation sequence en1v8n en5v/3vn mode (internal pin) offn activation activation shutdown shutdown shutdown deep shutdown presn vcc debounce
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 13 of 32 nxp semiconductors TDA8035HN smart card interface 8.7 activation sequence the following sequence then occurs with crystal oscillator (see figure 8 ): t = 64 toscint(freq high) 1. cmdvccn is pulled low (t0) 2. crystal oscillator st art up time (t0). 3. the internal oscillator changes to its high frequency & dc/dc starts (t1 = t0 + 768 tosc_low) 4. v cc rises from 0 to selected vcc value ( 5 v, 3 v, 1.8 v ) with a controlled slope (t 2 =t 1 + 3t/2) 5. i/o, aux1 and aux2 are enabled (t 3 =t 1 + 10t) (they were pu lled low until this moment) 6. clk is applied to the c3 contact (t 4 = t 3 + x) with 200 ns < x < 10 x 1/fxtal 7. rst is enabled (t 5 =t 1 + 13t). fig 8. activation sequence at t3 001aan752 3 ms oscint cmdvccn xtal1 vup vcc io clk rst t0 t1 t2 t3 t4 t5 t / 2 low frequency high frequency
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 14 of 32 nxp semiconductors TDA8035HN smart card interface 8.8 deactivation sequence when a session is completed, the micro-controller sets the cmdvccn line to the high state. the circuit then executes an automa tic deactivation sequence by counting the sequencer back and ends in the inactive state (see figure 9 ): 1. rst goes low (t 11 = t 10 + 3t/64) 2. clk is stopped low (t 12 =t 11 +t/2) 3. i/o, aux1 and aux2 are pulled low (t 13 =t 11 + t) 4. v cc falls to zero (t 14 =t 11 + 3t/2) (the deactivation sequence is completed when v cc reaches its inactive state) 5. vup falls to zero (t 15 =t 11 + 7t/2) 6. v cc < 0.4 v (t de = t 11 + 3t/2 + vcc fall time) 7. all card contacts become low-imped ance to gnd (i/ouc, aux1uc and aux2uc remain pulled up to v dd(intf) via a 10 k resistor). 8. the internal oscillator goes back to its lower frequency. 8.9 vcc regulator v cc buffer is able to continuously deliver up to 65ma at vcc = 5 v, 65 ma at vcc = 3 v, 35 ma at vcc =1.8 v . it has an internal overload detection at approximately 125 ma. this detection is internally f iltered, allowing spurious current pulses of some ms up to 200 ma to be drawn by the card without ca using a deactivation. (the average current value must stay below maximum). fig 9. deactivation sequence oscint cmdvccn rst clk i/o vcc vup xtal1 low frequency high frequency 001aan753 t10 t11 t12 t13 t14 t15 t / 2
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 15 of 32 nxp semiconductors TDA8035HN smart card interface 8.10 fault detection the following fault conditions are monitored by the circuit: 1. short-circuit or high current on v cc 2. card removal during transaction 3. v ddp or v dd(intf) or vreg dropping 4. overheating. there are two different cases (see figure 10 on page 16 ): 1. cmdvccn high: (outside a card session) then , offn is low if the card is not in the reader, and high if the card is in the reader. a supply voltage drop on v ddp is detected by the supply supervisor, generates an internal power-on reset pulse, but does not act upon offn. the card is not powered-up, so no short-circuit or overheating is detected. 2. cmdvccn low: (within a card session) then, offn falls low in any of the aforementioned cases. as soon as the fault is detected, an emergency deactivation is automatically performed. when the system co ntroller sets cmdvccn back to high, it may sense offn again after complete deactivation sequence in order to distinguish between a hardware problem or a card extr action (offn will then go back high if the card is still present). depending on the type of card presence switch within the connector (normally close or normally open), and on the mechanical ch aracteristics of the switch, a bouncing may occur on presn signal at card insertion or withdrawal. consequentl y, a debounce feature of approximately 4.05 ms (t deb = 1280 1/(fosc(int)_low) is in tegrated in the device. figure 11 on page 16 when the card is inserted, offn goes high only at the end of the debouncing time. when the card is extracted, an automatic d eactivation sequence of the card is performed on the first true/false transition on presn, and offn goes low .
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 16 of 32 nxp semiconductors TDA8035HN smart card interface fig 10. emergency deactivation sequence (card extraction) fig 11. behavior of offn, cmdvccn, presn and vcc oscint presn rst offn clk i/o vcc vup xtal1 low frequency high frequency 001aan754 t10 = t11 t12 t13 t14 t15 t / 2 001aan757 tdeb deactivation caused by cards withdrawal tdeb deactivation caused by short circuit offn cmdvccn vcc presn
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 17 of 32 nxp semiconductors TDA8035HN smart card interface 9. limiting values all card contacts are protected against any short with any other card contact. stress beyond these levels may cause permanent damage to the device. this is a stress rating only and functional operation of the device under this condition is not implied. 10. thermal characteristics table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ddp power supply voltage ? 0.3 6 v v dd(intf) interface supply voltage ? 0.3 4.1 v v ih high-level input voltage cs, presn, cmdvccn, clkdiv2, clkdiv1, en_1.8vn, en_5v/3vn, rstin, offn, poradj, xtal1, i/ouc, aux1uc, aux2uc, v ddp , v dd(intf) ? 0.3 4.1 v i/o, rst, aux1, aux2 and clk ? 0.35.75v t amb ambient temperature ? 25 +85 c t stg storage temperature ? 55 +150 c t j junction temperature +125 c p tot total power dissipation t amb = ? 40 to +85 c0.45w v esd electrostatic discharge voltage human body model (hbm) on card pins i/o, rst, v cc , aux1, clk, aux2, presn within typical application ? 10 +10 kv human body model (hbm) on all other pins ? 2+2kv machine model (mm) on all pins ? 200 +200 v field charged device model (fcdm) on all pins ? 500 +500 v table 6. thermal characteristics symbol package name parameter conditions typ unit r th(j-a) hvqfn32 thermal resistance from junction to ambient in free air with 4 thermal vias on pcb 55 k/w in free air without thermal vias on pcb 63 k/w
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 18 of 32 nxp semiconductors TDA8035HN smart card interface 11. characteristics table 7. characteristics of ic v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb =25 c; unless otherwise specified symbol parameter conditions min typ max unit supply voltage v ddp power supply voltage 2.7 3.3 5.5 v v dd(intf) interface supply voltage 1.6 3.3 3.6 v i ddp power supply current deep shutdown mode; f xtal = stopped -0.13 a shutdown mode; f xtal = stopped - 300 500 a active mode; clk = f xta /2; v cc = +5 v; no load --5ma active mode; clk = f xtal /2 ; v cc = +5 v; i cc = 65 ma --220ma active mode; clk = f xtal /2 ; v cc = +3 v; icc = 65 ma --160ma active mode; clk=f xtal /2 ; v cc = +1.8 v; i cc = 35 ma --120ma i dd(intf) interface supply current deep shutdown mode f xtal = stopped; present card --1 a shutdown mode f xtal = stopped; present card --1 a v th( vreg ) v th threshold voltage internal voltage regulator falling 1.38 1.45 1.52 v v hys( vreg ) v hys hysteresis voltage internal voltage regulator 90 100 110 mv v th(vddp) v th threshold voltage pin v ddp falling 2.15 2.25 2.35 v v hys(vddp) v hys hysteresis voltage pin v ddp 90 100 110 mv t w pulse width 3 6.5 8.9 ms v th(l)(poradj) low-level threshold voltage on pin poradj external resistors on poradj 0.68 0.86 1.04 v v hys(poradj) v hys hysteresis voltage pin poradj 30 60 90 mv i l leakage current pin poradj ? 1- 1 a v reg v o output voltage 1.62 1.8 1.98 v t r rise time exit of deep shutdown mode - - 200 s vup ( dc/dc converter) v oh output voltage v cc = 5 v, i cc < 65 ma dc 5.10 5.60 6.10 v v cc = 3 v, i cc < 65 ma dc 3.50 3.95 4.40 v v cc = 1.8 v, i cc < 35 ma dc 5.10 5.60 6.10 v card supply voltage (v cc ) (2 ceramic multilayer capacitances with low esr 220 nf/220nf should be used in order to meet these specs) [1]
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 19 of 32 nxp semiconductors TDA8035HN smart card interface c dec decoupling capacitance connected on v cc (220 nf + 220 nf 10 % ) 396 - 484 nf v o output voltage inactive mode; no load ? 0.1 - +0.1 v inactive mode; i o =1ma ? 0.1 - +0.3 v i o output current inactive mode & at grounded pin v cc -- ? 1ma v cc supply voltage active mode; 5 v card; i cc <65ma dc 4.75 5.0 5.25 v active mode; 3 v card; i cc <65ma dc 2.85 3.05 3.15 v active mode; 1.8 v card; i cc <35ma dc 1.71 1.83 1.89 v active mode; current pulses of 40 nas with i cc <200ma, t<400ns; 5v card 4.65 5.0 5.25 v active mode; current pulses of 40 nas with i cc <200ma, t<400ns; 3v card 2.76 - 3.20 v active mode; current pulses of 15 nas with i cc < 200 ma, t < 400 ns;1.8 v card 1.66 - 1.94 v v ripple(p-p) peak to peak ripple voltage from 20 khz to 200 mhz - - 350 mv i cc supply current v cc = 0 v to 5 v, 3v - - 65 ma v cc = 0 v to 1.8v - - 35 ma sr slew rate 5 v card 0.055 0.18 0.8 v/ s 3 v card 0.040 0.18 0.8 v/ s 1.8 v card 0.025 0.18 0.8 v/ s crystal oscillator (xtal1 and xtal2) c ext external capacitance connected on pins xtal1/xtal2 (depending on specification of crystal or resonator used) - - 33 pf f xtal crystal frequency 2 - 27 mhz f xtal1 external frequency applied on xtal1 with 56 pf serial capacitor 0 - 27 mhz v il low-level input voltage ? 0.3 - 0.3 v dd(intf) v v ih high-level input voltage 0.7v dd(in tf) - v dd(intf) + 0.3 v table 7. characteristics of ic ?continued v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb =25 c; unless otherwise specified symbol parameter conditions min typ max unit
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 20 of 32 nxp semiconductors TDA8035HN smart card interface t r(i) , t f (i) input rise time, input fall times f clk = f xtal1 = 20 mhz on external clock --4ns f clk = f xtal1 = 10 mhz on external clock --8ns f clk = f xtal1 = 5 mhz on external clock - - 16 ns data lines (pins i/o, i/ouc, aux1, aux2, auxiuc, aux2uc ) t d delay time falling edge on pins i/o and i/ouc or i/ouc and i/o --200ns t w(pu) pull-up pulse width 200 400 ns f max maximum frequency on data lines - - 1 mhz c i input capacitance on data lines - - 10 pf data lines to the card (pins i/o, aux1, aux2); (i ntegrated 10k pull up resistor connected to v cc ) v o output voltage inactive mode; no load 0 - 0.1 v inactive mode; i o =1ma 0 - 0.3 v i o output current inactive mode & at grounded pin i/o -- ? 1ma v ol low-level output voltage i ol =1ma 0 - 0.3 v i ol 15 ma v cc ? 0.4 - v cc v v oh high-level output voltage no dc load 0.9 v cc -v cc +0.1 v i oh < ? 40 a 5 v or 3 v 0.75 v cc v cc +0.1 v i oh < ? 20 a 1.8 v card 0.75 v cc v cc +0.1 v i oh ? 15 ma 0 - 0.4 v v il low-level input voltage ? 0.3 - 0.8 v v ih high-level input voltage v cc = +5 v 0.6vcc - v cc + 0.3 v v cc = +3 v or 1.8 v 0.7vcc - v cc + 0.3 v v hys hysteresis voltage on i/o 30 75 120 mv i il low-level input current on i/o; v il = 0 - - 600 a i lh high-level leakage current on i/o; v ih =v cc --10 a t r(i) , t f (i) input rise time, input fall time from v il max to v ih min - - 1.2 s t r(o) , t f(o) output rise time, output fall time c l <= 80 pf; 10 % to 90 % from 0 to v cc --0.1 s r pu pull-up resistance connected to v cc 8k 10k 12k i pu pull-up current v oh =0.9v cc , c = 80 pf ? 8 ? 6 ? 4ma data lines to the system; pins i/o c, aux1 c, aux2 c (integrated 10k pull up resistor to v dd(intf) ) v ol low level output voltage i ol =1ma 0 - 0.3 v table 7. characteristics of ic ?continued v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb =25 c; unless otherwise specified symbol parameter conditions min typ max unit
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 21 of 32 nxp semiconductors TDA8035HN smart card interface v oh high level output voltage no dc load 0.9 v dd(intf) -v dd(intf) + 0.1 v i oh 40 a; v ddi >2v 0.75 v dd(intf) -v dd(intf) + 0.1 v i oh 20 a; v ddi <2v 0.75 v dd(intf) -v dd(intf) + 0.1 v v il low-level input voltage ? 0.3 - 0.3 v dd(intf) v v ih high-level input voltage 0.7 v dd(intf) v dd(intf) + 0.3 v v hys hysteresis voltage on i/ouc 0.05 v dd(intf) - 0.25 v dd(intf) v i lh high-level input leakage current v ih =v ddi 10 a i il low-level input current v il =0 600 a r pu pull-up resistance connected to v dd(intf) 8k 10k 12k t r(i) , t f (i) input rise & fall times from v il max to v ih min - - 1.2 s t r(o) , t f(o) output rise & fall times c l 30 pf; 10 % to 90 % from 0 to v dd(intf) --0.1 s i pu pull up current v oh =0.9v dd , c = 30 pf ? 1- - ma internal oscillator f osc(int) internal oscillator frequency inactive state : osc(int)_low 230 315 430 khz active state : osc(int)_high 2.0 2.5 3.0 mhz reset output to the card (rst) v o output voltage inactive mode; no load 0 - 0.1 v inactive mode; i o =1ma 0 - 0.3 v i o output current inactive mode & at grounded pin rst -- ? 1ma t d between rstin and rst rst enabled - - 200 ns v ol low level output voltage i ol = 200 a,v cc = +5 v 0 - 0.3 v i ol = 200 a,v cc = +3 v or 1.8 v 0- 0.2v i ol = 20 ma (current limit) v cc ? 0.4 - v cc v v oh high level output voltage i oh = ? 200 a 0.9 v cc -v cc v i oh = ? 20 ma (current limit) 0 - 0.4 v tr, tf rise and fall time c l = 100 pf v cc = +5 v and +3 v --0.1us tr, tf rise and fall time c l = 100 pf v cc = +18 v --0.2us clock output to the card (clk) v o output voltage inactive mode; no load 0 - 0.1 v inactive mode; i o = 1 ma 0 - 0.3 v table 7. characteristics of ic ?continued v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb =25 c; unless otherwise specified symbol parameter conditions min typ max unit
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 22 of 32 nxp semiconductors TDA8035HN smart card interface i o output current inactive mode & at grounded pin clk -- ? 1ma v ol low level output voltage i ol = 200 a0-0.3v i ol = 70 ma (current limit) v cc ? 0.4 - v cc v v oh high level output voltage i oh = ? 200 a 0.9 v cc -v cc v i oh = ? 70 ma (current limit) 0 - 0.4 v t r rise time c l =30pf [2] - - 16 ns t f fall time c l =30pf [2] - - 16 ns f clk frequency on pin clk operational 0 - 20 mhz duty cycle c l =30pf [2] 45 - 55 % sr slew rate rise and fall; c l =30pf; v cc = +5 v 0.2 - - v/ns rise and fall; c l =30pf; v cc = +3 v 0.12 - - v/ns rise and fall; c l =30pf; v cc = +1.8 v 0.072 - - v/ns control inputs (pins cs, cmdvccn, clkdi v1, clkdiv2, rstin, en_5v/ 3vn, en_1.8vn) [3] v il low-level input voltage ? 0.3 - 0.3 v dd(intf) v v ih high-level input voltage 0.7 v dd(intf) -v dd(intf) + 0.3 v v hys hysteresis voltage on control input 0.05 v dd(intf) - 0.25 v dd(intf) v i ll low-level input leakage current v il = 0 - - 1 a i lh high-level input leakage current v ih = v dd(intf) --1 a card presence input (presn); presn has an integrated pull down resistor [3] v il low-level input voltage ? 0.3 - 0.3 v dd(intf) v v ih high-level input voltage 0.7 v dd(intf) -v dd(intf) + 0.3 v v hys hysteresis voltage 0.05 v dd(intf) -0.1 v dd(intf) v i ll low-level input leakage current v il = 0 - - 1 a i lh high-level input leakage current v ih = v dd(intf) --5 a offn output (pin offn is an nmos dr ain with a 10k pull up resistor to v dd(intf) ) v ol low level output voltage i ol =2ma 0 - 0.3 v v oh high level output voltage i oh = ? 15 a 0.75 v dd(intf) -v r pu pull-up resistance 8 10 12 k protections and limitations table 7. characteristics of ic ?continued v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb =25 c; unless otherwise specified symbol parameter conditions min typ max unit
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 23 of 32 nxp semiconductors TDA8035HN smart card interface [1] to meet these specifications, v cc should be decoupled to cgnd using two ceramic mult ilayer capacitors of low esr with values of either 220 nf. [2] the transition time and the duty factor definitions are shown in figure 12 on page 23 .; d=t1/(t1+ t2) [3] presn and cmdvccn are active low; rstin is active high; for clkdiv1 and clkdiv2 see table 4. t sd shutdown temperature at die - 150 - c i olim output current limit on pin i/o ? 15 - +15 ma on pin clk ? 70 - +70 ma on pin rst ? 20 - +20 ma on pin v cc = 5 v or 1.8 v 90 125 160 ma on pin v cc = 3 v 90 160 260 ma i sd shutdown current on pin v cc = 5 v or 1.8 v 80 115 150 ma on pin v cc = 3 v 80 150 250 ma timings t act activation time see figure 8 on page 13 1847 - 3390 s t deact deactivation time see figure 9 on page 14 35 90 250 s t act activation time time of the window for sending clk to the card with xtal1 1992 2690 3653 s t act(start) = t3; see figure 8 on page 13 t act(end )=t5; see figure 8 on page 13 2055 2766 3749 s t deb debouncing time on pin presn 2.96 4.05 5.55 ms table 7. characteristics of ic ?continued v ddp = 3.3 v; v dd(intf) = 3.3 v; f xtal = 10 mhz; gnd = 0 v; t amb =25 c; unless otherwise specified symbol parameter conditions min typ max unit fig 12. definition of output and input transition times fce66 6 10% 90% 90% 10% t r t f t 1 t 2 v oh (v oh + v ol ) /2 v ol
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 24 of 32 nxp semiconductors TDA8035HN smart card interface 12. application information (1) place close to the protected pin with good (low re sistive) and straight connection to the main ground. (2) place close to the supply pin with good (low resistive) and straight connection to gndp. (3) place close to tda8035s v cc pin with good connection to gndc. (4) place close to card connectors c1 (vcc) pinwidth good connection to gndc. (5) optional bridge. if not used, r1 must be o ohm and r2 absent (direct connection to vddi). (6) gndp and gndc must be connected to the main gr ound with a straight and low resistive connection fig 13. application diagram 001aan759 0 c2 100 nf (1) c9 (4) 220 nf c8 220 nf (3) r2 (5) r1 (5) c10 56 pf c1 100 nf (1) c4 330 nf c5 r 1 f (2) c3 330 nf c6 (2) 100 nf c7 (2) 10 f i/ouc 124 clk poradj 223 rst cmdvccn 322 vcc vdd(intf) vddi vddi 421 vup c5 c1 card connector c6 c2 c7 c3 c8 vddi c4 clkdiv1 520 sap clkdiv2 619 sbp en5v_3v 718 vddp vdd en_1.8v 817 sbm rstin microcontroller 932 aux2uc offn 10 31 aux1uc gnd 11 30 presn xtal1 12 29 cs xtal2 13 28 i/o vreg 14 27 aux2 sam 15 26 aux1 gndp 16 25 gndc tda8035 v dd(intf) v dd(intf)
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 25 of 32 nxp semiconductors TDA8035HN smart card interface 13. package outline fig 14. package outline sot617-7 references outline version european projection issue date iec jedec jeita sot617-7 - - - sot617-7_po 10-02-08 10-02-09 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 5.1 5.0 4.9 2.2 2.1 2.0 5.1 5.0 4.9 0.5 3.5 0.5 0.4 0.3 0.1 a dimensions note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. h vqfn32: plastic thermal enhanced very thin quad flat package; no leads; 3 2 terminals; body 5 x 5 x 0.85 mm sot617- 7 a 1 b 0.30 0.21 0.18 cd (1) d h e (1) e h 2.2 2.1 2.0 ee 1 e 2 3.5 lv 0.1 w 0.05 y 0.05 y 1 0 2.5 5 mm scale terminal 1 index area b a d e - - - c y c y 1 x detail x a c a 1 b e 2 e 1 e e 1/2 e 1/2 e a c b v c w terminal 1 index area d h e h l 1 16 9 25 32 8 24 17
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 26 of 32 nxp semiconductors TDA8035HN smart card interface 14. soldering 14.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface moun t ics, but it is not suitable for fine pitch smds. in these situations re flow soldering is recommended. 14.2 reflow soldering reflow soldering requires solder paste (a sus pension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for ex ample, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c small/thin packages. 14.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following cond itions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. ? for packages with leads on two sides and a pitch (e): ? larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direct ion of the printed-circuit board; ? smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of th e printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circ uit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured.
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 27 of 32 nxp semiconductors TDA8035HN smart card interface typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 14.5 package related soldering information [1] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . [2] these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). [3] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [4] wave soldering is only suitable for lqfp, qfp and tqfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [5] wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 15. abbreviations table 8. suitability of surface mount ic packages for wave and reflow soldering methods package soldering method wave reflow [1] bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable [2] suitable plcc [3] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [3] [4] suitable ssop, tssop, vso not recommended [5] suitable table 9. abbreviations acronym description esd electrostatic discharge
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 28 of 32 nxp semiconductors TDA8035HN smart card interface 16. revision history table 10. revision history document id release date data sheet status change notice supersedes TDA8035HN v. 1.0 20110419 product data sheet - -
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 29 of 32 nxp semiconductors TDA8035HN smart card interface 17. legal information 17.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 17.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 30 of 32 nxp semiconductors TDA8035HN smart card interface quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comple te, exhaustive or legally binding. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 17.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 18. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
TDA8035HN all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 1.0 ? 19 april 2011 31 of 32 nxp semiconductors TDA8035HN smart card interface 19. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .3 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 4. clock configuration . . . . . . . . . . . . . . . . . . . . . .10 table 5. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .17 table 6. thermal characteristics . . . . . . . . . . . . . . . . . .17 table 7. characteristics of ic . . . . . . . . . . . . . . . . . . . . 18 table 8. suitability of surface mount ic packages for wave and reflow soldering methods . . . . . . 27 table 9. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 20. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 2. pin configuration hvqfn32 . . . . . . . . . . . . . . . . .5 fig 3. block voltage supervisor . . . . . . . . . . . . . . . . . . . .8 fig 4. voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9 fig 5. voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9 fig 6. switch external clock . . . . . . . . . . . . . . . . . . . . . .10 fig 7. shutdown mode and deep shutdown mode . . . .12 fig 8. activation sequence at t3 . . . . . . . . . . . . . . . . . .13 fig 9. deactivation sequence . . . . . . . . . . . . . . . . . . . .14 fig 10. emergency deactivation sequence (card extraction) . . . . . . . . . . . . . . . . . . . . . . . . .16 fig 11. behavior of offn, cmdvccn, presn and vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 fig 12. definition of output a nd input transition times . . .23 fig 13. application diagram . . . . . . . . . . . . . . . . . . . . . . .24 fig 14. package outline sot617-7 . . . . . . . . . . . . . . . . .25
nxp semiconductors TDA8035HN smart card interface ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 19 april 2011 document identifier: TDA8035HN please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 protection of the contact smart card . . . . . . . . 1 2.2 easy integration into your contact reader . . . . . 1 2.2.1 other. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 7 8.1 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.2 voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 8 8.3 clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.4 i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.5 cs control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8.6 shutdown mode and deep shutdown mode . 12 8.7 activation sequence . . . . . . . . . . . . . . . . . . . . 13 8.8 deactivation sequence . . . . . . . . . . . . . . . . . . 14 8.9 vcc regulator . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.10 fault detection . . . . . . . . . . . . . . . . . . . . . . . . 15 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 10 thermal characteristics . . . . . . . . . . . . . . . . . 17 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18 12 application information. . . . . . . . . . . . . . . . . . 24 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 25 14 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.1 introduction to soldering surface mount packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14.2 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 26 14.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 27 14.5 package related solderin g information . . . . . . 27 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 16 revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 17 legal information. . . . . . . . . . . . . . . . . . . . . . . 29 17.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 29 17.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18 contact information. . . . . . . . . . . . . . . . . . . . . 30 19 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 20 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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